As is known, phase change memory (PCM) arrays are based upon memory elements which use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated to two different crystallographic structures of the material forming the memory element, and precisely an amorphous, disorderly phase and a crystalline or polycrystalline, orderly phase. The two phases are hence associated to resistivities of considerably different values.
Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as calcogenides or calcogenic materials, can be used advantageously in phase change memory cells. The currently most promising calcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is now widely used for storing information on overwritable disks.
In the calcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa. In the amorphous state, moreover, the resistivity depends to a marked extent upon the temperature, with variations of approximately one order of magnitude every 100° C. with a behavior typical of P-type semiconductors.
Phase change can be obtained by locally increasing the temperature. Below 150° C., both the phases are stable. Above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the calcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then rapidly cool off the calcogenide.
From the electrical standpoint, it is possible to reach the crystallization and melting temperatures by causing a current to flow through a resistive element (also called a heater) that heats the calcogenic material by the Joule effect. FIG. 1 illustrates, in a simplified way, the behavior of the resistance of a calcogenic material as a function of the heating current and the logic values associated thereto, wherein RR indicates the resistance corresponding to the amorphous state (reset state or logic “0”) and RS indicates the resistance corresponding to the crystalline or polycrystalline state (set state or logic “1”).
The programming curve of a phase change memory element is shown in FIG. 2. Curve A represents the behavior of a PCM element in the reset state (high resistivity) and curve B represents the behavior of a PCM element in the set state (low resistivity), when a voltage of an increasing value is applied.
As shown, when a voltage higher than a threshold value (Vth) is applied to an element in the reset state, with Vth being a function of the material and the geometry of the element, the cell changes its state and switches from the high resistivity curve A to the low resistivity curve B.
When the cell is in the set state along curve B, it is necessary to apply a voltage/current pulse of suitable length and high amplitude (greater than Vreset/Imelt) so as to cause the element to switch to the amorphous phase associated to a high resistivity. The resetting pulse should be interrupted in a short time (quench time) of about 1–10 ns.
To bring the element in the set state (so as to cause crystallization of the calcogenic material and thus switching to a low resistivity state) it is necessary to apply a voltage/current pulse of a suitable length and amplitude (portion of curve B comprised between I1 and I2), however avoiding any quenching and allowing the element to cool slowly.
FIG. 3 shows the current amplitudes (IS, IR) of typical set and reset current pulses and the respective set and reset time lengths (tS, tR).
The structure of a phase change memory array using a calcogenic element as a storage element is shown in FIG. 4. The memory array 1 of FIG. 4 comprises a plurality of memory cells 2, each including a memory element 3 of the phase change type and a selection element 4 formed here by an NMOS transistor. Alternatively, the selection element 4 may be formed by a bipolar junction transistor or a PN diode.
The memory cells 2 are arranged in rows and columns. In each memory cell 2, the memory element 3 has a first terminal connected to an own bitline 11 (with addresses BLn−1, BLn, . . . ), and a second terminal connected to a first conduction terminal of an own selection element 4. The selection element 4 has a control terminal connected to an own control line, also referred to as wordline 12 (with addresses WLn−1, WLn, . . . ), and a second conduction terminal connected to ground.
For biasing the memory element 3 belonging to a specific cell 2, for example the one connected to the bitline BLn−1 and to the wordline WLn−1, to a suitable voltage (V2−V1), the bitline 11 connected to the selected cell is brought to a first voltage V1 and the wordline 12 connected to the selected cell is brought to a high voltage, so that the second terminal of the memory element 2 is biased to a second voltage V2 close to zero.
Writing is effected by applying to a selected cell the current pulses shown in FIG. 3.
The application of the constant current pulses of FIG. 3 is however disadvantageous since variations in the manufacturing process may cause a considerable variation in the current requested for programming a memory cell. The programming current depends on the contact area between the calcogenic material and the heater; in particular, bigger contact areas require higher programming currents and vice-versa. As a matter of facts, the requested programming current ranges between I1 and I2 in FIG. 2, considering a safety margin. Thus, the application of a single programming current value may not be able to ensure programming of all the memory cells (all bits).
U.S. Pat. No. 6,487,113 describes a method for programming a phase-change memory with a short quench time based on applying a high current pulse to all the cells, to bring them in a first state, decreasing some of the currents to lower levels at sufficiently high rates to cause the corresponding cells to be programmed to the first state and decreasing the other currents at sufficiently low rates to cause the other cells to be programmed to a second state.
The above solution allows the quench time to be reduced, but has the drawback of requiring a complex and bulky programming circuit. The programming circuits shown therein also dissipate high currents.